SÉMINAIRE GIGL : Silicon Photonic Interconnects - Minimizing the Controller Latency

Titre : Silicon Photonic Interconnects: Minimizing the Controller Latency

Conférencier : Felipe Gohring de Magalhães, Ph.D.

Résumé : Design trends for the next-generation multiprocessor systems point to the integration of a large number of processing cores, requiring high-performance interconnects. One solution to improve the communication infrastructure in such systems is to use networks-on-chip (NoCs) as they present considerable improvement in the system bandwidth and scalability. Nevertheless, as the number of integrated cores continues to increase, metallic interconnects in NoCs become a performance bottleneck due to their higher latency, lower bandwidth, and higher power consumption when the system scales. Optical interconnection networks (OINs) are one of the most promising paradigms in this design context, addressing the aforementioned issues with the metallic interconnect. A critical requirement to realize high-performance OINs is to develop low-latency controllers for such systems. Control techniques, such as those based on circuit-switching, can impose a high latency while performing the correct network routing, and hence a better solution must be found in order to fully utilize OINs. This work overview some of the common control techniques employed in OINs. Low-latency approaches for OIN control are presented. They reduce the overall system communication latency through granting different requests within a few clock cycles.

Biographie : Felipe obtained a Computer Engineering/Science PhD on a cotutelle agreement between PUCRS (Pontifical Catholic University of Rio Grande do Sul) and Polytechnique Montréal. His Master’s Degree was obtained in 2010 from PUCRS as well as a bachelor’s degree in Computer Engineer in the same institution. Has experience in the area of Computer Engineering/Science with emphasis on embedded systems, having worked on the following topics: design and development of embedded real-time operating systems, implementation of multi-processor architectures and intra-chip communication infrastructure, such as buses, networks-on-chip and optical integrated networks.

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